.\"	$OpenBSD: piixpcib.4,v 1.4 2007/10/08 12:48:21 jmc Exp $
.\"
.\" Copyright (c) 2007 Stefan Sperling <stsp@stsp.in-berlin.de>
.\"
.\" Permission to use, copy, modify, and distribute this software for any
.\" purpose with or without fee is hereby granted, provided that the above
.\" copyright notice and this permission notice appear in all copies.
.\"
.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
.\"
.Dd $Mdocdate: October 8 2007 $
.Dt PIIXPCIB 4 i386
.Os
.Sh NAME
.Nm piixpcib
.Nd Intel PIIX4 ISA bridges
.Sh SYNOPSIS
.Cd "piixpcib* at pci?"
.Cd "isa* at piixpcib?"
.Sh DESCRIPTION
The
.Nm
driver supports Intel
.Tn 82371AB
and
.Tn 82440MX
PIIX4 ISA bridges.
.Pp
Besides the core functionality, the
.Nm
driver provides support for the first generation of Intel's SpeedStep
technology present in some Pentium III CPUs.
It allows the user to manually control CPU frequency with the
.Xr sysctl 8
program.
The
.Xr apmd 8
daemon can be used to automatically control CPU frequency.
SpeedStep provides two CPU power states, low and high.
The driver will switch the CPU into low power state if the
.Va hw.setperf
sysctl is less than or equal to 50,
and into high power state if it is greater than 50.
.Sh SEE ALSO
.Xr cpu 4 ,
.Xr ichpcib 4 ,
.Xr intro 4 ,
.Xr isa 4 ,
.Xr pci 4 ,
.Xr apmd 8 ,
.Xr sysctl 8
.Sh HISTORY
The
.Nm
driver first appeared in
.Ox 4.2 .
.Sh BUGS
The driver sometimes fails to update the hw.cpuspeed sysctl correctly
after switching power state.
The reason is that there seems to be
no reliable way to determine CPU frequencies corresponding to low
and high power states, so the driver has to rely on the p3_update_cpuspeed
function to dynamically determine CPU speed after switching power state.
This seems to fail occasionally, especially if interrupt load of the system
is high.
Note that this bug is purely cosmetic.
Switching power state still
works even if the CPU speed is displayed incorrectly.